Mythic is seeking experienced RTL Design Engineers to design and implement RTL for next-generation AI processors. You will work on a novel digital dataflow architecture, including scheduling subsystems, interconnect fabrics, and DMA engines, driving high performance and efficiency.
The team collaborates with architecture, custom analog IP, compiler, verification, emulation, and post-silicon groups to ensure seamless integration. 8+ years in RTL design and strong Verilog skills are highly valued.
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