Senior RTL Design Engineer - AI Accelerator ASIC

SambaNova Systems is seeking an experienced RTL Design Engineer to own blocks within an RDU ASIC subsystem. You will contribute to microarchitecture, write and debug SystemVerilog, and guide blocks through implementation, tape-out, and silicon bring-up in collaboration with verification and physical design teams.

The role requires strong SystemVerilog skills, a solid digital logic foundation, and experience with power, performance, and area trade-offs on high-speed ASICs.