Senior RTL Architect for AI Accelerator Hardware

River AI Inc. is seeking exceptional RTL design engineers to architect and implement high-performance AI accelerator hardware.

You will define architecture, micro-architecture, and implementation for SoCs on advanced nodes, owning large parts of the chip and coordinating with compiler, performance model, verification, and physical design teams. Based in Austin or Palo Alto, you will collaborate across stacks to optimize throughput, latency, and power, contribute to ECOs and silicon-at-scale