Tektronix is seeking an experienced ASIC Layout Design Engineer to perform block and chip-level layout of high-performance RF analog ASICs, collaborating with design engineers and layout teams. You will ensure smooth product flow from development to mass production, driving yield and test-time improvements.
The role requires 7+ years in RF/Analog/Mixed-Signal layout, proficiency with Cadence Virtuoso and PDKs across multiple foundries, and strong skills in layout planning, routing, and
#J-18808-LjbffrSenior RF/Analog ASIC Layout Engineer - Bonus Eligible in boulder at Unknown Company
This position is listed as full time and onsite.