Senior Principal Technologist – Memory

Senior Principal Technologist – MemoryAre you passionate about pushing the boundaries of system, memory, software, and chip architecture? Do you thrive when pitching cutting-edge technology solutions to customers and industry partners? We are seeking a creative customer facing Technologist to help facilitate Astera's development of data center memory solutions.

In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in system architecture, SOC memory sub-system architecture, PCIe/CXL technologies, DRAM/memory architecture, and hardware-software co-design. You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers' bottlenecks in hyperscale data centers.This role is fully in person, in San Jose. Some travel may be required.Basic qualifications:BS in Electrical or computer engineering, MS or PhD preferred.?10 year's experience developing memory-related solutions and integrating them into systems/racks for data centersDeep experience with PCIe 5/6, and CXL including protocol level depthExpertise in OS software integration including memory allocation/managementRecent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc)Deep expertise and understanding of memory components (DRAM, etc)Strong understanding of datacenter system architecture and design challengesStrong understanding of "full stack" solutions from silicon to application integrationExperience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business casesAbility to dig deeply into technical challenges and use casesExcellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners.Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment.Willingness to travel occasionally for customer meetings and industry events.Preferred experience:Expertise in JEDEC-defined memory interface specificationsExpertise in memory ECC and error handlingExperience in product integration with BIOS, kernel, OS, tooling, and BMCsExperience with board and system designExisting engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc.Hands-on silicon development experienceSalary range is $205,000 to $255,000 depending on experience, level, and business need.

This role is eligible for discretionary bonus, incentives and benefits.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.