Senior Principal RTL Verification Architect

Cadence is seeking a Senior Engineer in the System Verification Group in California to advance Xcelium RTL/logic simulation for next‑gen hardware verification. You will architect features, optimize performance in C/C++, and collaborate with a distributed team to deliver high‑quality results.

You will apply deep knowledge of RTL/logic simulation, SDC constraints, and timing analysis, while contributing to robust unit tests and specifications in a fast‑moving environment.