Celero Communication Inc. is seeking a Principal/Senior High-Speed Analog Layout Engineer to drive layout for ADCs, DACs, PLLs and other high-performance blocks.
You will lead cross-functional layout efforts, mentor engineers across time zones, and ensure first-pass silicon success through rigorous checks. This hands-on role requires strong Cadence/Calibre experience, deep device physics understanding, and proven leadership in complex IP layout at FinFET nodes.
#J-18808-LjbffrSenior/Principal High-Speed Analog Layout Architect (Remote) in irvine at Unknown Company
This position is listed as full time and onsite.