Senior Principal Engineer Digital ASIC Design/Manager

Senior Principal Engineer Digital ASIC DesignJoin Kyocera International, Inc. We're hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility!Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education, skills, and market factors)With nearly 80,000 employees worldwide, Kyocera is a global leader in advanced ceramic technologies used in aerospace, automotive, medical, and semiconductor industries. Our materials power everything from smartphones to space shuttles — and we're just getting started.We don't just offer jobs — we offer careers with purpose, stability, and growth. Here's what you can expect:Generous Time Off3 weeks of vacation to start (120 hours/year)10 paid holidays annuallyFinancial WellnessCompetitive pay401(k) with company matchEmployer-paid pension planComprehensive Health CoverageMedical, dental, and vision insuranceLife insuranceFlexible Spending Account (FSA)Employee Assistance Program (EAP)Investing in YouTuition reimbursementPaid time off to volunteerFlexible schedulesWork-Life Balance & CultureOnsite gyms, walking tracks, and employee gardens at larger locationsLong-tenured team (many with 30+ years of service!)Inclusive and diverse workforceA company philosophy rooted in doing the right thing as a human beingKyocera's culture is deeply inspired by our founder, Dr. Kazuo Inamori. His values guide our decisions and shape our workplace.

Learn more about our guiding principles here:Kyocera ValuesReady to Make a Difference? Apply today and become part of a team that's shaping the future — one innovation at a time.Exempt: Yes Safety Sensitive: No Department: TUBIS Reports To: Not indicatedGeneral Description of PositionResponsible for architecture of digital design. Plan and implement digital infrastructure. Plan, oversee, and execute implementation, verification, emulation, and validation of design. Identify potential high-risk areas and present possible resolutions. Drive methodology process and requirement specification documents.

Work with external vendors and internal teams in developing plans for micro-architecture, verification, and emulation of digital modules.Essential Duties and ResponsibilitiesLead digital design projects from inception to production for mixed signals ICs.Hire and manage full-time employees or contractors to support projects.Participate in RFIC design flow by architecting and designing digital control functionality which interfaces to I/O and analog functions.Perform RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, AMBA bus, state machine, memories, embedded processor cores (RISC-V), bus arbitration, DMA, registers, IO pads, synchronous, asynchronous access and control functions.Perform project resource planning, detailed schedule development, milestone and task trackingOversee PNR and ensure integrity of physical layer design.Perform/oversee test plan development, digital verification, coverage analysis, and post silicon lab test.Support mixed signal verification of design.Perform/oversee scan insertion, MBIST and LBIST.Perform any other related duties as required or assigned.Requirements/QualificationsBS or MS degree in Electrical Engineering with 15 years of industry experience in Digital ASIC design in complex multi-million gate architectures and deep submicron technologies, with majority of products with 1st silicon successProven technical leadership experienceAbility to work with cross-functional teams and contractors across geographical boundariesStrong verbal, communication and organizational skillsAbility to improve digital design methodology to deliver high quality ICs on scheduleExperience with requirements development, design reviews and documentationExperience with mixed-signal design methodologySystem level experience with architectural tradeoffs for partitioning functions across software, embedded firmware, and custom RTL based hardware accelerators.Experience with architectural tradeoffs for selecting/defining high-speed communication interfacesExperience with the selection and integration of embedded processor cores (RISC-V or similar), memory systems, priority interrupt controller, etc.Ability to perform area and power estimationExperience with test plan development for pre-silicon verification/emulation and post silicon validationSolid understanding of DFT architecture and familiarity with production test methodsIn depth knowledge and extensive hands-on experience in digital RTL design (Verilog/System Verilog) and micro-architecture, linting, LEC, RDC/CDC, SDF gate simulation, revision control and tagged releases, scripting, bug tracking, synthesis, scan insertion, timing constraint development, floor planning, clock tree synthesis, timing closure, netlist ECOs, and digital verification.Experience with foundry provided CMOS process and design kits, standard cell libraries and memory compilersExperience setting up toolchains (compiler, debugger, etc.) for embedded processor coresExperience developing embedded firmware (C and assembly language) for embedded processor cores for digital verificationExperience with co-simulation to verify debug interface operability with the tool chainExperience with Synopsys and Cadence front-end and back-end tools, such as: Xcelium, Genus, Conformal, Innovus, Synopsys PrimeTime, Spyglass Lint, TetraMaxAbility to perform/oversee post silicon bench test of digital functionsExperience with UVM is a plusExperience with digital design for PLL control/calibration is a plusExperience with interfacing to ADC/DAC, trim/calibration algorithms and DSP is a plusThe above statements are intended to describe the work being performed by people assigned to this job. They are not intended to be an exhaustive list of all responsibilities, duties and skills required. The duties and responsibilities of this position are subject to change and other duties may be assigned or removed at any time. This position may require exposure to information subject to US export control regulations, i.e. the International Traffic in Arms Regulation (ITAR) or the Export Administration Regulations (EAR).Kyocera International, Inc. values diversity in its workforce, and is proud to be an AAP/EEO employer.

All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Kyocera International, Inc.'s Human Resources team directly. Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.Equal Opportunity Employer This employer is required to notify all applicants of their rights pursuant to federal employment laws. For further information, please review the Know Your Rights notice from the Department of Labor.