Asteralabs is looking for a Senior Principal Digital Design Engineer to lead next-generation digital designs for AI infrastructure connectivity in San Jose, California. This high impact role involves defining micro-architecture strategies and guiding chip-level design decisions. You will work with various teams to ensure the design meets performance and quality standards.
Preferred candidates will have a Bachelor’s degree in Electrical Engineering, extensive experience in SoC products, and a proven track record of successful designs. The role offers a competitive salary, potentially between $205,000 to $255,000 based on experience.
#J-18808-Ljbffr