Senior Principal ASIC Design Lead – High-Perf Networking

Hewlett Packard Enterprise is seeking an Senior Principal ASIC Design Engineer to lead an important ASIC subsystem from concept through tape‑out. This onsite role sits in California and involves collaboration with product, hardware, software, verification, and physical design teams.

You will design high‑density networking ASICs using Verilog/SystemVerilog, drive timing closure, power and area trade‑offs, and mentor engineers while advancing automation and AI‑assisted design techniques.