Senior PLL Design Engineer — RF & Clocking

Samsung Semiconductor Inc. (SSI) seeks a Senior/Staff PLL Designer to craft PLLs and clocking subsystems for RF transceivers and SerDes in advanced CMOS tech.

You’ll model, verify, and characterize PLLs, collaborating with digital, layout and systems teams to hit performance, power and area goals. The role requires a Master’s with 2+ years or PhD with 0 years, strong Spectre/SpectreRF/AMS, Matlab/Simulink, and Verilog/SystemVerilog skills, plus lab phase-noise and jitter experience.