Celero Communications, Inc. is seeking a senior to principal PLL Design Engineer to architect and implement high-speed CMOS PLLs for next‑gen optical transceivers and SerDes in Irvine or San Jose, CA.
The role emphasizes clocking circuits, VCOs, charge pumps, and loop filters with extensive layout supervision and lab bring‑up. Requirements include a Master’s or PhD in Electrical Engineering with 5+ years in PLL design, experience with 16/12/7nm nodes, Cadence Virtuoso, EMX/HFSS, and MATLAB.
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