Senior PLL Design Architect for High-Speed Transceivers

Celero Communications, Inc. seeks a Principal PLL Design Engineer to lead high-speed clocking circuit development for next-generation optical transceivers and SerDes. You will architect and implement PLLs, analyze phase noise, and guide tape-out efforts.

You should have a Master’s or PhD in EE with 5+ years in PLL design, experience with 16nm–2nm nodes, Cadence Virtuoso, EMX/HFSS, and MATLAB. Excellent communication is essential, with a track record of production-level designs.