Samsung Semiconductor Inc. in San Jose, CA, is seeking a Senior/Staff PLL Designer to develop high-performance PLLs and clocking subsystems for RF transceivers and high-speed I/O in deep-submicron CMOS.
You will collaborate with digital and software teams, perform system modeling, verification, and production support, and contribute to layout and lab testing to meet stringent requirements.
#J-18808-LjbffrSenior PLL & Analog Designer (RF/Serdes) in san jose at Unknown Company
This position is listed as full time and onsite.