Amazon's Annapurna Labs seeks a Sr. Physical Design Verification Engineer to lead full chip verification efforts and collaborate with layout teams in Cupertino/Austin. You will drive methodologies, tape-out readiness, and mentorship, shaping cloud silicon excellence.
The role requires deep scripting, backend flow experience, and a proven record of successful tape-outs on advanced nodes. Strong cross-team communication is essential in a fast-paced environment.
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