TSMC Technology Inc. seeks a seasoned Physical Design Verification Lead to drive end‑to‑end verification for CPU blocks toward production tapeouts on N7 or below tech nodes. You will partner with the STA team and lead ECOs for tight timing closure, while addressing EM/Noise and Power/IR challenges.
You will supervise CTS and P&R strategies, optimize block floorplans, and mentor junior engineers, delivering silicon‑quality results at a customer site in the South Bay area.
#J-18808-LjbffrSenior Physical Design Verification Lead - CPU Blocks Tapeouts in san jose at Unknown Company
This position is listed as full time and onsite.