We are seeking a skilled Physical Design Engineer to implement high-performance RISC-V based processor designs from RTL to GDSII. The role involves full-chip and block-level physical implementation, timing closure, power optimization, PPA and sign-off.
Qualification and Required skills:
- Atleast 8 Years of Experience in Block-level physical implementation from RTL to GDSII
- Own advanced physical design tasks including: EM/IR and power grid optimization for high-current blocks, Congestion mitigation and routing-aware floorplanning and Clock tree synthesis and skew management across domains.
- Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk).
- Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.