Senior Physical Design Engineer: RTL-to-GDSII Expert

Altera is seeking a Senior Physical Design Engineer to drive the implementation of custom IP and SoC designs through GDSII, enabling manufacturing-ready silicon. You will lead timing closure, power optimization, and signoff while collaborating with RTL, DFT, and CAD teams to deliver high-quality ASIC/FPGA products.

Responsibilities include S&T, CTS, clocking, and reliability analyses, with strong emphasis on automation and methodology improvements.