Celero Communications, Inc. is seeking a Senior/Principal Physical Design Engineer to lead RTL-to-GDSII implementation for complex SoCs. The role spans San Jose, Irvine, and remote work options, with responsibility for floorplanning, CTS, EM/IR cleanup, and signoff readiness.
You will collaborate with architects, logic designers, and analog teams to ensure tapeout readiness while driving automation and robust design flows using Tcl/Python/Perl.
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