Technical-Link N. America is seeking a seasoned Physical Design professional to drive power-grid and clock constraint strategies across chip layers. You will debug LVS/DRC issues at both chip and block levels and contribute to the tape-out readiness with close collaboration with foundries.
The ideal candidate has deep experience with physical design verification, CDC/STA methodologies, and mixed-signal environments, using Caliber and Redhawk for power analysis and assurance.
#J-18808-LjbffrSenior Physical Design Engineer: Power, Clock & Tape-out in san jose at Unknown Company
This position is listed as full time and onsite.