Wipro is seeking a Physical Design Engineer to drive block-level design from netlist to GDSII with strong PnR, PPA optimization, and timing convergence. Expect hands-on CTS, routing, EMIR, and STA methodologies, collaborating with RTL/DFT teams to ensure successful tapeouts.
Qualifications include BS/MS in EEE, experience across 7nm/5nm nodes, and proficiency with Fusion Compiler/ICC2, PrimeTime, and Innovus. Competitive compensation and full benefits offered.
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