Senior Physical Design Engineer: Place & Route (On‑Site)

Asteralabs in San Jose, California, is looking for a Physical Design Engineer (Place & Route) to play a crucial role in the design of connectivity ASICs used globally.

This on-site generalist role demands a strong background in electrical engineering and at least 8 years of experience in complex SoC design. Candidates should be hands-on with synthesis, timing closure, and possess expertise in CAD tools such as Cadence or Synopsys.

The role offers a competitive salary ranging from $160,000 to $230,000, depending on level and experience, plus equity and benefits.