Intel seeks a senior physical design engineer to drive integration of chiplet and advanced packaging technologies. You will lead floorplanning, timing constraints, and PnR cycles to meet power and performance targets while collaborating with RTL designers.
Asynchronous design and AI-assisted automation are key growth areas. Applicants should have multi-silicon tape-outs and strong scripting in Perl/TCL/Python, plus Cadence and Synopsys tool experience.
#J-18808-LjbffrSenior Physical Design Engineer Neuromorphic AI Chips in santa clara at Unknown Company
This position is listed as full time and onsite.