Senior Physical Design Engineer – FPGA SoC Innovator

Altera in San Jose, CA seeks a Senior Physical Design Engineer to drive implementation of IP and SoC designs from RTL to GDSII, optimizing PPA and delivering signoff for next-generation FPGA products. You will work with RTL, CAD, DFT, timing, and verification teams to execute synthesis, floorplanning, CTS, STA, and a full physical design flow, aiming for robust power, performance, and area characteristics.

The role requires substantial hands-on experience with advanced EDA tools and a track