Eridu, a Silicon Valley-based hardware startup, seeks a senior SoC physical design engineer for the San Francisco Bay Area. You will own the physical implementation of complex SOCs, from floorplanning to signoff, and collaborate with micro-architects to optimize PPA for 7nm or below processes.
Applicants should have 10+ years in EE, strong CAD skills (Synthesis, Place & Route), Verilog/SystemVerilog, and hands-on experience with Innovus or Fusion Compiler.
#J-18808-LjbffrSenior Physical Design Engineer - AI Silicon (7nm) in san francisco at Unknown Company
This position is listed as full time and onsite.