Capgemini Engineering in Santa Clara, CA is seeking a seasoned Physical Design Engineer to advance complex digital/mixed-signal IC implementations through floor planning, placement, CTS, routing, and tape-out readiness. You will optimize power, area, and performance while collaborating with cross-functional teams across the design lifecycle.
Key qualifications include 10+ years in physical design, proficiency with LVS/DRC, CDC, STA, and parasitic delay analyses, and hands-on use of Virtuoso,
#J-18808-LjbffrSenior Physical Design Engineer – Advanced Node in santa clara at Unknown Company
This position is listed as full time and onsite.