Capgemini Engineering in Santa Clara, CA is seeking a Physical Design Engineer to drive complex digital and mixed-signal IC implementation from floorplanning to tape-out.
The role emphasizes hands-on physical design across advanced process nodes (3nm–7nm), power-grid and clock constraints, LVS/DRC verification, and cross-functional collaboration with design, layout, and verification teams to meet performance, power and area targets.
#J-18808-LjbffrSenior Physical Design Engineer – Advanced Node ICs in santa clara at Unknown Company
This position is listed as full time and onsite.