Capgemini Engineering in Santa Clara, CA, is seeking a Senior Physical Design Engineer to drive complex IC implementations at advanced nodes. You will lead floorplanning, placement, clock tree synthesis, routing and power-grid strategies, collaborating across teams to meet timing, power and area goals, and ensure tape-out readiness.
The role requires 10+ years in physical design, LVS/DRC debugging, CDC and timing analysis, and hands-on use of Virtuoso, Calibre and similar EDA tools.
#J-18808-LjbffrSenior Physical Design Engineer - Advanced Node ICs in santa clara at Unknown Company
This position is listed as full time and onsite.