Capgemini Engineering is seeking a senior Physical Design Engineer in a on-site Santa Clara location to drive complex digital/mixed-signal IC implementation from floorplanning through tape-out.
You will lead design activities, optimize power-grid strategies, perform LVS/DRC checks, and collaborate with cross-functional teams to meet PPA goals for 3nm–7nm nodes. Strong ADM/EDA tool expertise is required.
#J-18808-LjbffrSenior Physical Design Engineer – Advanced-Node IC in california at Unknown Company
This position is listed as full time and onsite.