TSMC - Taiwan Semiconductor Manufacturing Company Limited in San Jose, California, is seeking an Advanced Physical Design and Verification Engineer to lead DRC/LVS/antenna checks and fix PDV/EMIR/Noise/SigEM issues. The role includes timing ECOs on high-performance blocks and customizing clocks within a hybrid work setup.
You will report to the Manager of the Advanced Chip Implementation team and join a team driving cutting-edge semiconductor technology.
#J-18808-LjbffrSenior Physical Design & Verification Engineer in california at Unknown Company
This position is listed as full time and hybrid.