Annapurna Labs (U.S.) Inc. in Austin, TX, is seeking an ASIC Physical Design Methodology Engineer to lead design and verification innovation for ML accelerator chips. You will drive PPA improvements and collaborate across RTL, PD, and DFT teams to deliver scalable, high-quality flows.
The role requires strong scripting in TCL, Python, Perl, and C++, plus hands-on use of PD tools like Innovus, ICC2, and Fusion Compiler. This position offers competitive compensation and benefits.
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