Senior PCIe Subsystem RTL Architect

TylSemi, Inc. in San Jose, CA seeks a Principal PCIe Subsystem RTL lead to own the PCIe microarchitecture from PHY to MAC and TL. You will lead integration of third-party PCIe IP, define lane configurations, and drive the TL pipeline across multiple operating modes.

The role requires deep PCIe expertise, SystemVerilog RTL skills, and experience with chiplet-based designs. Join a fast-paced team delivering scalable PCIe infrastructure for AI/HP systems.