Senior PCIe IP Design Lead (RTL/SystemVerilog)

Rambus in the United States is seeking a motivated Principal Design Engineer to join the PCIe IP design team. You will contribute to architecture and micro-architecture and implement designs in SystemVerilog, collaborating with an international team.

The role involves prototyping IPs on cutting-edge FPGAs, supporting existing IP generations, and working in a hybrid environment with three onsite days per week. A strong RTL background and Masters/PhD are preferred.