A leading recruitment firm is looking for a Package Design Engineer to take responsibility for complex flip-chip-BGA package designs in a collaborative environment focusing on high-speed SerDes, AI, and HPC applications. The ideal candidate will have significant experience in package design along with skills in Cadence tools. This full-time role is based in San Jose, California and offers a chance to work on cutting-edge semiconductor projects.
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Senior Package Design Engineer for High-Speed ASICs in san jose at Unknown Company
This position is listed as full time and onsite.