Senior NoC Interconnect RTL Engineer – Relocation & Hybrid

OpenAI is looking for a highly experienced RTL engineer to lead the design of critical on- and off-chip interconnect components for their custom AI accelerator platform. This senior role involves driving architecture through the silicon lifecycle, optimizing performance, and mentoring junior engineers.

The ideal candidate will have extensive experience in SoC design and RTL engineering, particularly in high-performance computing environments. The position offers a hybrid work model based in San Francisco, along with relocation assistance.