Intel seeks a senior physical design engineer to drive innovation at the intersection of advanced semiconductor tech and neural-inspired computing. You will guide chiplet integration, physical packaging, and block- and chip-level closure while collaborating with RTL designers to meet timing and power targets.
The role requires multi‑year tape‑outs experience, scripting in Perl/TCL/Python, and familiarity with Cadence/Synopsys tools. A hybrid work model is offered within the US.
#J-18808-LjbffrSenior Neuromorphic Physical Design Engineer (Hybrid) in folsom at Unknown Company
This position is listed as full time and hybrid.