Senior ML TPU SoC RTL Design Architect

Google is seeking a senior hardware engineer to drive RTL design and microarchitecture for ML IP within Google Silicon SoCs. You will collaborate across hardware and software teams to deliver high-performance, power-efficient accelerators and cohesive subsystem integration.

The role includes leading RTL development, timing and power estimation, and silicon bring-up on FPGA and final silicon. In-person interviews are expected; preferred locations include Mountain View, CA and San Diego, CA.