Google seeks a Senior TPU Design Engineer, Silicon, to advance ML IPs for Google Silicon SoCs. You will drive microarchitecture, RTL, and integration for high‑performance ML accelerators, collaborating with cross‑functional teams to push performance and efficiency.
Based in Mountain View or San Diego, you will lead design efforts, mentor juniors, and navigate ASIC flows from RTL to tape-out, focusing on timing, power, and quality.
#J-18808-LjbffrSenior ML TPU IP Architect - SoC Designer (Equity & Bonus) in jasper at Unknown Company
This position is listed as full time and onsite.