Senior ML Silicon/TPU Design Engineer

Google is seeking a Senior TPU Design Engineer, Silicon, in Mountain View, CA. You will lead RTL design and microarchitecture for ML accelerators, drive IP/SoC development, and collaborate with hardware, software, and ML teams to deliver high-performance silicon.

The role emphasizes leadership of IP/SoC design efforts, experience with ARM-based SoCs, interconnects, and ASIC methodology, and a track record of delivering complex silicon projects on schedule. In-person interviews are typical.