Google is seeking a Hardware Architect for silicon development in Mountain View. You will contribute to ML IPs for Google Silicon SoCs and define microarchitectures, data flows, and integration needs for subsystems.
Lead RTL activities, run functional and performance simulations, and support customers through schedules and bring-up. The role requires extensive RTL experience with Verilog/SystemVerilog, leadership of IP/SoC teams, and strong ASIC methodology.
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