NVIDIA is seeking a Senior Mask Design Engineer to contribute to the detailed layout of silicon interposers for NVIDIA products. You will collaborate with PTL and I/O signal integrity teams to deliver tight-schedule packages using Cadence tools.
The role requires a BS in Electrical Engineering, 5+ years of mask/layout experience, deep CMOS layout knowledge, and Cadence Virtuoso expertise, plus scripting and verification tool familiarity.
#J-18808-LjbffrSenior Mask & Interposer Design Engineer in workfromhome at Unknown Company
This position is listed as full time and onsite.