Lattice Semiconductor, with a strong presence in San Jose, seeks a senior engineer to lead IP/sector integration for FPGA platforms. You will drive RTL/debug flows, SDC/STA, and DFT integration, coordinating across IP, product engineering, and test teams to ensure robust sign-off.
The ideal candidate has 15+ years in ASIC/SoC/FPGA, strong Verilog/SystemVerilog expertise, and experience with Cadence Virtuoso and SPICE simulations.
#J-18808-LjbffrSenior IP & FPGA Integration Engineer in san jose at Unknown Company
This position is listed as full time and onsite.