Senior IO/Clocking Design Engineer, DRAM

Micron Technology in Boise, Idaho, invites a Principal IO/Clocking Design Engineer to push the speed limits of high‑speed circuits used in DRAM products. You will design, optimize, verify, and fan out IO and clocking paths, develop modeling methods, and collaborate with Product Engineering and SI teams to align silicon performance with specs.

This senior role requires MSEE with 10+ years or BSEE with 12+ years, proficiency in Cadence, UNIX, and strong communication; mentoring and scripting