Synopsys Inc is seeking an experienced ASIC Verification Engineer in Austin to own verification of PCIe, CXL, DDR, and Ethernet Interface IP. You will architect and implement scalable UVM environments, define test plans, and drive coverage-driven verification from spec through release.
The role requires 8–10+ years of hands-on verification with SystemVerilog, strong debugging skills, and collaboration with architecture, RTL, firmware, and systems teams.
#J-18808-LjbffrSenior Interface IP Verification Lead in austin at Unknown Company
This position is listed as full time and onsite.