A cutting-edge technology company in Austin is seeking a Design Verification Engineer to join their Interface IP DV team. The role involves collaborating with architects and vendors to ensure IP correctness and performance. Candidates should have over 5 years of design verification experience, alongside expertise in UVM/SystemVerilog and industry-standard IP interfaces. This position offers competitive benefits including housing subsidies and relocation support. Interactions with the team in San Jose are expected during certain months.
#J-18808-Ljbffr
#J-18808-Ljbffr
Senior Interface IP Verification Engineer in austin at Unknown Company
This position is listed as full time and onsite.