Senior Interconnect Architect for TileLink NoC

SiFive is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOCs. You will build highly configurable RTL generators in Chisel/Scala, accelerating time‑to‑market and performance.

You will collaborate with verification teams, implement TileLink interconnects, manage cache coherence, and contribute to documentation and tooling within SiFive's Chisel/FIRRTL framework.