Senior Interconnect Architect for TileLink & Chisel RTL

SiFive is looking for a principal-level hardware engineer to enhance CPU and interconnect development. Applicants should have a background in RISC-V architecture and experience in RTL design. The role also involves working on scalable and customizable architectural solutions.

With a strong emphasis on collaboration, engineers will architect innovative designs that integrate efficiently within the existing framework. Competitive benefits and compensation are included.