Senior Full-Chip Timing Engineer: Modeling & Integration

Altera seeks a Full Chip Timing Modeling and Integration Engineer to develop timing methodologies and execute full-chip timing for next-generation FPGA products. You will work with cross-functional teams to define timing strategies, generate high-level models, and ensure timing model integration and validation.

The role emphasizes hands-on STA, design constraint development, and ongoing process improvements within a fast-paced, multi-site environment in San Jose, CA.