Senior FPGA Verification Engineer (SystemVerilog/UVM)

A global test and automation company is seeking a Digital Logic Verification Engineer in Reading, MA. The role focuses on FPGA verification and requires 3+ years of experience in digital logic verification. Ideal candidates should have strong knowledge of System Verilog, UVM, and common IP protocols. The position offers competitive compensation ranging from $98,700 to $157,900, alongside a discretionary bonus plan and comprehensive health benefits.
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