Senior FPGA Verification Engineer - SystemVerilog & UVM

Teradyne is seeking a Digital Functional Verification Engineer to drive planning, strategy, and execution of challenging FPGA verification projects. You will work under the supervision of a Verification Lead, interfacing with Hardware, Software, and Applications teams to ensure robust designs.

The role requires a strong background in SystemVerilog/UVM, verification planning, and Xcelium/Simvision tooling, with experience in standard protocols and IP integration.